The invention relates generally to a method for fabricating a semiconductor device. More particularly, the invention relates to a method for fabricating a semiconductor device using an exposure mask.
As design rules of semiconductor devices have been radically reduced, gate resistance values of cell transistors increases. As a result, there is a limit to a planar transistor structure with respect to the gate resistance and threshold voltage. Methods for securing a channel length without an increase in design rules have been studied. In order to expand the channel length while maintaining a low critical dimension (“CD”) of a gate, recess channel structures have been researched. In the recess channel structure, a semiconductor substrate is recessed, and a gate is formed over the recessed semiconductor substrate to extend an effective channel length.
FIGS. 1 and 2 are views illustrating a prior art method for fabricating a semiconductor device. A device isolation structure 12 that defines an active region 14 is formed over a semiconductor substrate 10. A portion of active region 14 is etched by a photolithography process with a line-type mask pattern (not shown) to form a recess region 16. A gate oxide film (not shown) is formed over active region 14 and in recess region 16. A gate polysilicon layer (not shown), a tungsten layer (not shown), and a gate hard mask layer (not shown) are sequentially formed over active region 14 and recess region 16. The gate hard mask layer, the tungsten layer, and the gate polysilicon layer are patterned by a photolithography process with a gate mask, to form a recess gate (not shown).
Due to the high level integration in semiconductor devices, the critical dimension (“CD”) and process margin of active region 14 in its longitudinal direction are lacking as shown in FIG. 2. When recess region 16 is formed, the edge of neighboring active region 14 is damaged at location “A,” which causes a device malfunction.